Memory with shared bit lines

ABSTRACT

A memory block comprising a network of memory cell rows and columns, each memory cell being connected to a word line and at least one bit line, in which at least two word lines are associated with each row, and at least two adjacent columns share at least one same bit line, two memory cells of the two adjacent columns belonging to a same row being connected to different word lines.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to memories comprising anetwork of memory cell rows and columns and the associated memory cells.

[0003] 2. Discussion of the Related Art

[0004]FIG. 1 schematically shows a cell of a static memory of randomaccess type (SRAM) of conventional structure. The memory cell comprisesinverters 1, 2, connected in antiparallel. The respective inputs ofinverters 1, 2 are connected to respective bit lines BL, {overscore(BL)} via switches 3, controlled by a row selection signal conveyed by aword line WL. Each inverter 1, 2, is powered by a high voltage VDD and alow voltage GND, currently the ground.

[0005] To write an information in the memory cell, a voltage VDD isapplied on one of bit lines BL or {overscore (BL)}, and a voltage GND isapplied on the other one. Then, switches 3 are turned on to set thestate of the inputs and outputs of inverters 1 and 2. Switches 3 arethen turned off and the state of the signals across inverters 1 and 2 ismaintained.

[0006] To read an information from the memory cell, each bit lines BLand {overscore (BL)} is precharged to a voltage ranging between voltagesVDD and GND, after which switches 3 are turned on so that the voltageson the bit lines vary according to the state of the signals acrossinverters 1 and 2. A sense amplifier (not shown) connected to the bitlines provides a binary information in relation with the informationkept in the memory cell.

[0007] Inverter 1 comprises a P-channel MOS transistor, PI1, in serieswith an N-channel MOS transistor, NI1. The source of transistor PI1 isconnected to voltage VDD and the source of transistor NI1 is connectedto voltage GND. The drains of transistors PI1 and NI1 are connected at apoint O2. The gates of transistors PI1 and NI1 are also connected at apoint O1.

[0008] Similarly, inverter 2 comprises transistors PI2 and NI2 connectedlike transistors PI1 and NI1, the gates of transistors PI2 and NI2 beingconnected to terminal O2 and the common drains of transistors PI2 andNI2 being connected to terminal O1. Switches 3 are formed of MOStransistors M1 and M2, generally with an N channel.

[0009]FIG. 2 shows a portion of a conventional SRAM, each memory cellbeing represented by a reference block MCij. 8 cells have been shown,with i varying from 0 to 1 and j varying from 0 to 3. Conventionally, asingle word line (WLi, i varying from 0 to 1) corresponds to a memorycell row and two bit lines (BLj and {overscore (BLj)}, j varying from 0to 3) correspond to a memory cell column.

[0010] In such a memory, upon writing or reading of data into or from amemory cell, it is necessary to select, with one of word lines WL0, WL1,all the memory cells in the row where the searched memory cell ispresent. This results in a consumption which increases with the numberof memory cells forming each row.

[0011]FIG. 3 shows a memory in which four word lines are associated witheach row, each word line being connected to one memory cell out of four.Generally, if a memory comprises N word lines per row, the number ofmemory cells simultaneously selected by a word line will be divided byN. By reducing the number of memory cells selected upon each writeand/or read operation, the memory consumption is decreased.

[0012] However, the increase in the number of word lines per row causesan increase in the memory surface area.

[0013] As an illustration, FIG. 4 schematically shows an example of atopology of cell MC01 of the memory of FIG. 3, in which the electriccircuit of FIG. 1 and the additional word lines are formed in atechnology with one polysilicon level and three metallization levels.Other polysilicon and metallization levels may be present and used.

[0014] The surfaces delimited by a thin line correspond to active areasof the semiconductor substrate or to polysilicon strips deposited on thesubstrate and corresponding to the gates of MOS transistors. Althoughthe view is not drawn to scale, the relative dimensions and positions ofeach region are kept to show the real bulk of the integrated circuit.The double lines correspond to metal strips of level one. The horizontalthick black lines correspond to metal strips of level two, and thevertical thick black lines correspond to metal strips of level three.The crosses show contacts connecting, through the insulating layerslocated between the metallization levels and the polysilicon level,metal strips to active areas or to polysilicon strips or viasconnecting, through the insulating layers located between themetallization levels, metal strips to other metal strips. For clarity,the metal strips are not shown with surface areas proportional to thesurface areas of the active areas. However, the position of each lineconforms to the real position of the corresponding metal strip in theintegrated circuit.

[0015] In FIG. 4, the different elements shown in FIG. 1 can be seen.The gate, source, and drain regions of the various transistors aredesignated with letter G, S, or D followed with the transistorreference.

[0016] Gates GM1 and GM2 of the respective MOS transistors M1 and M2correspond to portions of polysilicon strip 10. Active area 11corresponds to MOS transistor M1, to MOS transistor NI2, and to theconnection between these transistors. Similarly, active area 12corresponds to MOS transistor M2, to MOS transistor NI1, and to theconnection between these transistors. The respective gates GNI2 and GPI2of MOS transistors NI2 and PI2 correspond to portions of polysiliconstrip 13. Similarly, the respective gates GNI1 and GPI1 of MOStransistors NI1 and PI1 correspond to portions of polysilicon strip 14.

[0017] The different metal strips of level one, two, and three are usedto connect the active areas and the polysilicon strips to obtain theequivalent electric diagram shown in FIG. 1. In particular, the wordline connected to gates GM1, GM2 of transistors M1 and M2 is, in thepresent example, word line WL01 corresponding to a horizontal metalstrip of level two which is connected to polysilicon strip 10 via avertical metal strip 17 of level one.

[0018] The topology of such a cell imposes for word lines WL00, WL01,WL02, and WL03 to correspond to horizontal metal strips of level two,while word lines BL1 and {overscore (BL1)} correspond to vertical metalstrips of level three. To enable passing of the word lines, it isnecessary to increase the surface area of each cell and thus the totalsurface area of the memory. In a manufacturing technology in which thesmallest pattern has a length of 0.18 μm, a width Δx of 2.16 μm, aheight Δy of 5.24 μm, and a surface area of 11.32 μm² are obtained forthe memory cell of FIG. 4. As a comparison, a memory cell of similartopology but with a single word line per row would have a width Δx of2.16 μm, a height Δy of 3.6 μm, and a surface area of 7.78 μm²

SUMMARY OF THE INVENTION

[0019] The present invention aims at providing an alternative memoryarchitecture and associated memory cell topology.

[0020] The present invention aims at providing a memory having a surfacearea which does not vary when the number of word lines per rowincreases. In particular, the present invention aims at providing amemory, with several word lines per row, having a general surface areasmaller than the surface area of an equivalent memory of conventionalstructure with a single word line per row or of the same order.

[0021] To achieve these objects, the present invention provides a memoryblock comprising a network of memory cell rows and columns, each memorycell being connected to a word line and at least one bit line, in whichat least two word lines are associated with each row, and at least twoadjacent columns share at least one same bit line, two memory cells ofthe two adjacent columns belonging to a same row being connected todifferent word lines.

[0022] According to an embodiment of the present invention, the memorycells are formed in a semiconductor substrate, and comprise transistors,the gates of which correspond to a same polysilicon level and theinterconnections of which are formed by conductive strips distributed onthree levels, the conductive strips forming the word lines being oflevel three, and a conductive strip forming a bit line being of leveltwo.

[0023] According to an embodiment of the present invention, each memorycell, arranged between two other memory cells of the same row, isconnected to two supply lines of different voltages, each supply linebeing shared between the memory cell and one of the adjacent memorycells, and placed on a common edge between the two memory cells.

[0024] According to an embodiment of the present invention, the supplylines are of level two, parallel to the bit line, and orthogonal to theword lines.

[0025] According to an embodiment of the present invention, each memorycell, arranged between two other memory cells of the same row, comprisesfour N-channel MOS transistors having their sources and drains formed ina same active area and aligned along a common edge between the memorycell and one of the adjacent memory cells.

[0026] According to an embodiment of the present invention, each memorycell, arranged between two other memory cells of the same row, comprisestwo P-channel MOS transistors having their sources and drains alignedalong a common edge between the memory cell and one of the adjacentmemory cells.

[0027] According to an embodiment of the present invention, the memorycells comprise a conductive strip of level two, perpendicular to theword lines, connected to one of the word lines and to two MOStransistors.

[0028] According to an embodiment of the present invention, each memorycell comprises a transistor connected to the bit line, and a metal stripof level one connecting a transistor to a bit line located on anadjacent cell of the same row.

[0029] According to an embodiment of the present invention, each memorycell, arranged between the two other memory cells of the same column,comprises a metal strip of level one, connecting a transistor to asupply line or to a bit line, the metal strip being shared between thememory cell and one of the adjacent memory cells, and placed on a commonedge between the two memory cells.

[0030] According to an embodiment of the present invention, at least onememory cell comprises a conductive strip of level two, parallel to thebit line and located above the P-channel MOS transistors.

[0031] The present invention also provides a memory formed of a networkof rows and columns of memory blocks in which the word lines associatedwith memory cell rows of memory blocks of a same memory block row arecommon, the bit lines associated with memory cell columns of memoryblocks of a same memory block column are separate, and comprising, permemory block column, at least one additional bit line extending in thecolumn direction and being likely to be connected to one of the adjacentbit lines.

[0032] The foregoing objects, features and advantages of the presentinvention, will be discussed in detail in the following non-limitingdescription of specific embodiments in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033]FIG. 1, previously described, schematically shows a conventionalSRAM cell;

[0034]FIG. 2, previously described, schematically shows a conventionalSRAM with one word line per row;

[0035]FIG. 3, previously described, schematically shows a conventionalSRAM with four word lines per row;

[0036]FIG. 4, previously described, schematically shows an example of aconventional topology of a cell of a SRAM with four word lines per row;

[0037]FIG. 5 schematically shows a SRAM according to the presentinvention with four word lines per row;

[0038]FIG. 6 shows an embodiment of a memory cell according to thepresent invention;

[0039]FIG. 7 shows a simplified cross-section view of FIG. 6 along lineVII-VII;

[0040]FIG. 8 shows a simplified cross-section view of FIG. 6 along lineVIII-VIII;

[0041]FIG. 9 shows a simplified cross-section view of FIG. 6 along lineIX-IX;

[0042]FIG. 10 schematically shows a SRAM divided into sub-blocks; and

[0043]FIG. 11 shows an alternative of the memory of FIG. 6.

DETAILED DESCRIPTION

[0044] For clarity, same elements are designated with same references inthe different drawings.

[0045]FIG. 5 shows a SRAM with four word lines per row. The columnsshare, two by two, two bits lines, BL0-{overscore (BL0)} andBL1-{overscore (BL1)}. Each bit line is thus connected, for each row, tothe switches of two adjacent memory cells. Thus, for example, whenmemory cell MC00 is selected by word line WL00, write and/or readoperations can be performed in the memory cell directly from bit linesBL0 and {overscore (BL0)} since memory cell MC01, also connected tothese bit lines, is not selected.

[0046]FIG. 6 shows a simplified view of an example of topology of memorycell MC01 of FIG. 5. As for the memory cell of FIG. 4, the technologyused to form the electric circuit is a technology with one polysiliconlevel and three metallization levels, knowing that other polysilicon andmetallization levels may be present and used. The same conventions asfor FIG. 4 are used, except that, in FIG. 6, the horizontal thick blacklines correspond to metal strips of level three and the vertical thickblack lines correspond to metal strips of level two.

[0047] The four N-channel MOS transistors M1, NI1, NI2, and M2 areformed, in this order, in a same vertical active area strip located tothe left of the drawing. P-channel MOS transistors PI1 and PI2 areformed in independent active areas located to the right of the drawing.

[0048] Gate GM2 of MOS transistor M2 corresponds to a portion of apolysilicon strip 20. Gates GNI2 and GPI2 of MOS transistors NI2 and PI2correspond to portions respectively located at the opposite ends of apolysilicon strip 21. Gates GNI1 and GPI1 of transistors NI1 and PI1correspond to portions of a polysilicon strip 22. Finally, gate GM1 ofMOS transistor M1 corresponds to a portion of a polysilicon strip 23.

[0049] Supply lines VDD and GND are formed of vertical metal strips oflevel two which laterally delimit the memory cell. Supply line GND isarranged in the immediate vicinity of the active area comprising theN-channel MOS transistors.

[0050] Bit line {overscore (BL0)} corresponds to a vertical metal stripof level two substantially located above aligned transistors M2, NI2,NI1, and M1. A vertical metal strip 30 of level two, placed between bitline and supply line VDD is connected at its ends, by contacts and vias,to polysilicon strips 20 and 23, and thus to respective gates GM2, GM1of MOS transistors M2 and M1. Metal strip 30 is also connected by a viato a word line WL01.

[0051] Word lines WL00 to WL03 correspond to horizontal metal strips oflevel three and are uniformly distributed on the memory cell. Thisuniform distribution is possible due to the fact that no otherconnection uses the third metallization level.

[0052] MOS transistors PI2 and PI1 are vertically arranged andsubstantially aligned in an area delimited by vertical metal strip 30and supply line VDD. Source SPI2 of transistor PI2 is arranged towardsthe bottom of the memory cell, and source SPI1 of transistor PI1 isarranged towards the top of the memory cell. Source SPI2 of MOStransistor PI2 is connected to vertical supply line VDD via a contactand a via and a horizontal metal strip 31 of level one. Similarly,source SPI1 of MOS transistor PI1 is connected to supply line VDD via acontact and a via and a horizontal metal strip 32 of level one.

[0053] Drains DM2 and DNI2 of MOS transistors M2 and NI2 are connectedto a metal strip 33 of level one, itself connected both to drain DPI2 ofMOS transistor PI2 and to polysilicon strip 22. Drains DM1 and DNI1 ofMOS transistors M1 and NI1 are connected to a metal strip 34 of levelone, itself connected both to drain DPI1 of MOS transistor PI1 and topolysilicon strip 21.

[0054]FIG. 7 shows a cross-section view of FIG. 6 along line VII-VIIwhich extends along the active area containing the N-channel MOStransistors of the memory cell. Drain DM2 of MOS transistor M2 and drainDNI2 of MOS transistor NI2 correspond to a same region 40. Similarly,source SNI2 of MOS transistor NI2 and source SNI1 of MOS transistor NI1correspond to a same region 41. Finally, drain DNI1 of MOS transistorNI1 and drain DM1 of MOS transistor M1 correspond to a same region 42.

[0055] Sources SNI2, SNI1 of respective MOS transistors NI2, NI1, areconnected to vertical supply line GND via a contact, a via and ahorizontal metal strip 43 of level one; Source SM2 of MOS transistor M2is connected to vertical bit line {overscore (BL0)} via a contact 44 anda via 45 which join on a horizontal metal strip 46 of level one.

[0056] Source SM1 of MOS transistor M1 is connected to a bit line BL0(not shown) arranged on the adjacent memory cell located to the left ofthe memory cell shown in FIG. 6, via a contact, a via, and a horizontalmetal strip 47 of level one extending on the adjacent cell. The adjacentmemory cell can be obtained by 180° rotation (except for the viaconnected to word line WL01) or by symmetry with respect to supply lineGND (except for via 45 and for the via connected to word line WL01) ofthe shown memory cell, and is crossed by a vertical bit line BL0 oflevel two adjacent to supply line GND, which delimits the border betweentwo memory cells.

[0057]FIG. 8 shows a cross-section view of FIG. 6 according to lineVIII-VIII. As can more clearly be seen in this drawing, horizontalpolysilicon strip 20 is connected to one of the ends of vertical metalstrip 30 of level two by a contact 48 and a via 50. Similarly,horizontal polysilicon strip 23 is connected to the other end of metalstrip 30 by a contact 50 and a via 51. Metal strip 30 substantiallyextends under the four horizontal strips of level three corresponding toword lines WL00 to WL03, and is connected to word line WL01 by a via 52.

[0058]FIG. 9 shows a cross-section view of FIG. 6 along line IX-IX.Source SPI2 of MOS transistor PI2 can be seen to be connected, by acontact, to horizontal metal strip 31 of level one, and drain DPI1 ofMOS transistor PI1 can be seen to be connected, by a contact, tohorizontal metal strip 32 of level one. Drain DPI2 of MOS transistor PI2is connected, by a contact, to metal strip 33 of level one, and sourceSPI1 of MOS transistor PI1 is connected, by a contact, to metal strip 34of level one.

[0059] As clearly appears from FIGS. 7, 8, and 9, only horizontal wordlines WL00 to WL03 take up the third metallization level. Indeed, supplylines GND, VDD, bit line {overscore (BL0)} and metal strip 30 allcorrespond to vertical metal strips taking up the second metallizationlevel.

[0060] The fact of arranging sources SNI2 and SNI1 of respective MOStransistors NI2 and NI1 and sources SPI1 and SPI2 of respective MOStransistors PI1 and PI2 close to the lateral edges of the cell enablesplacing the metal strips of supply lines VDD and GND on the lateraledges of the cell. Supply line VDD can thus be put in common with thememory cell of the same row located to the right of the shown cell, andsupply line GND can be put in common with the memory cell of the samerow located to the left of the shown cell. Further, sources SM2 and SM1of respective MOS transistors M2 and M1, and sources SPI1 and SPI2 ofrespective MOS transistors PI1 and PI2 being close to the upper or loweredge of the cell, horizontal metal strips 31, 32, 46, 47 of level onecan be placed on the upper or lower edges of the memory cell. Metalstrips 31 and 46 and the associated vias and contacts can thus be put incommon with the memory cell of the same column located under the showncell, and metal strips 32 and 47 and the associated via and contacts canbe put in common with the memory cell of the same column located abovethe shown cell.

[0061] Upon forming of a memory, it is possible to divide the memoryinto memory sub-blocks. Each memory sub-block for example corresponds toa number of memory cell rows, since the bit lines of the memory cells ofa sub-block are not connected to the corresponding bit lines of anadjacent sub-block.

[0062]FIG. 10 schematically shows as an example a memory architecturewith four word lines per row divided into memory sub-blocks. Althoughthe drawing only shows one row per sub-block, it should be clear thateach sub-block comprises a great number of rows.

[0063] The memory comprises vertical global bit lines GBL0, {overscore(GBL0)}, GBL1, {overscore (GBL1)} parallel to the bit lines of thememory cells enabling connecting the bit lines of all sub-blocks to theread and write amplifiers, for example, as shown in FIG. 10, byextending over all the memory sub-blocks. In the present example, twoglobal bit line can be connected to the four bit lines of each sub-blockassociated with four adjacent memory cells. The connection is performedat the level of multiplexing cells via switches controlled by selectionlines SEL00, SEL01, SEL10, SEL11. Thus, in a read or write operation ina determined memory cell, only the two bit lines associated with thismemory cell are connected to the global bit lines. The charge seen bythe read and write amplifiers is thus limited to the charge present onthe bit lines of a sub-block and to the charge present on the global bitlines.

[0064] The addition of global bit lines GBL0, {overscore (GBL0)}, GBL1,{overscore (GBL1)} may, with conventional memory cell technologies,cause an increase in the memory surface area or require use ofadditional metallization levels. On the contrary, with the memory celltopology according to the present invention, the addition of global bitlines does not modify the memory surface area.

[0065]FIG. 11 shows an example of the topology of cell MC01 of thememory of FIG. 7. The topology corresponds to that of FIG. 6 to whichone vertical global bit line GBL0 of level two has been added. Thisvertical global bit line GBL0 is placed between vertical metal strip 30of level two and vertical supply line VDD of level two. It is possibleto add global bit line GBL0 without modifying the topology of the restof the memory cell since the memory cell according to the presentinvention, for a 0.18-μm technology, has a width Δx of 2.58 μm, due tothe arrangement of the active areas and of the polysilicon strips, thatis, more than the width of 2.16 μm of the memory cell of FIG. 4, andthis, for a same number of vertical metal strips (of level two in thepresent invention, and of level three for the memory cell of FIG. 4).

[0066] A cell height Δy of 2.88 μm is obtained, smaller than the 5.24-μmheight of the cell of FIG. 4, and even than the 3.6-μm height of a cellwith one word line per row according to a topology similar to that ofFIG. 4. Several factors take part in the height gain, especially: theputting in common of metal strips 31, 32, 46, 47 with the adjacentmemory cells of the same column; the vertical arrangement of thetransistors which enables placing in quincunx, along the verticaldirection, contacts 48, 50 and vias 49, 51 associated with the gates oftransistors M1 and M2 with respect to the contacts associated with thesources and drains of the same transistors; and the arrangement of theword lines on the third metal level, which enables running of four wordlines without modifying the memory cell height, whereby the presence ofthe word lines is not a limiting factor for the memory cell height,conversely to the topology of FIG. 4 where each addition of a word lineaccordingly increases the memory cell height.

[0067] It should also be noted that the arrangement of sources SNI1 andSNI2 of N-channel MOS transistors NI1 and NI2 along a same lateral edgeenables having one supply line GND only connected to the two N-channelMOS transistors NI1 and NI2, conversely to the memory cell of FIG. 4which comprises two supply lines GND, each connected to a single one ofN-channel MOS transistors NI1 and NI2. Any offset problem which couldoccur between the two supply lines GND is thus avoided.

[0068] Further, supply line VDD which would be horizontal on the memorycell of FIG. 4 is vertical in the present invention. Thus, when a memorycell is selected by a word line, supply line VDD supplies this memorycell only instead of supplying all the memory cells in the row havingalso been selected by the word line, thus avoiding a drop in the powersupply by consumption peaks, which can adversely affect the reading fromor the writing into a memory point, and may even cause a loss of theinformation memorized in the memory point in a reading.

[0069] A memory cell surface area of 7.43 μm², that is, 34% less thanthe 11.32-μm² surface area of the memory cell of FIG. 4 with four wordsper row, and even 4% less than a memory cell with one word line or rowof topology similar to that of FIG. 4 is thus obtained. The presentinvention thus enables keeping a surface of the same order withoutadding an additional metallization level to form the electric circuit,and thus without increasing the manufacturing cost and difficulties ascompared to prior art.

[0070] Of course, the present invention is likely to have variousalterations, modifications, and improvements which will readily occur tothose skilled in the art. Thus, P-channel MOS transistors PI1 and PI2,shown vertically in FIGS. 6 and 11, could be arranged horizontally sothat their respective sources are put in common with the P-channeltransistors of the memory cell of the same row located to the right ofthe shown cell. Further, the forming of the memory cell has beendescribed as implementing one polysilicon level and three metallizationlevels. It is quite possible to replace the metal strips of one orseveral metallization levels with another conductive material. Forexample, the first metallization level may be replaced with a level twoof doped polysilicon. Further, the memory point switches may be formedwith P-channel MOS transistors, making the necessary adaptations.Further, those skilled in the art will know how to adapt the presentinvention to any exiting type of memory, such as a random access memorywith memory cells having one bit line, a double or multiple accessrandom access memory (DPRAM), a content-addressing memory (CAM), adynamic random access memory (DRAM), or a ROM.

[0071] Such alterations, modifications, and improvements are intended tobe part of this disclosure, and are intended to be within the spirit andthe scope of the present invention. Accordingly, the foregoingdescription is by way of example only and is not intended to belimiting. The present invention is limited only as defined in thefollowing claims and the equivalents thereto.

What is claimed is:
 1. A memory block comprising a network of memorycell rows and columns, each memory cell being connected to a word line(WL00, WL01, WL02, WL03) and two bit lines (BL0, {overscore (BL0)}), inwhich at least two word lines are associated with each row, and at leasttwo adjacent columns share the two bit lines, two memory cells of thetwo adjacent columns belonging to a same row being connected todifferent word lines.
 2. The memory block of claim 1, wherein the memorycells are formed in a semiconductor substrate, and comprise transistors(M1, M2, NI1, NI2, PI1, PI2), the gates (GM1, GM2, GNI1, GNI2, GPI1,GPI2) of which correspond to a same polysilicon level and theinterconnections of which are formed by conductive strips distributed onthree levels, the conductive strips forming the word lines (WL00, WL01,WL02, WL03) being of level three, and a conductive strip forming a bitline (BL0, {overscore (BL0)}) being of level two.
 3. The memory block ofclaim 2, wherein each memory cell, arranged between two other memorycells of the same row, is connected to two supply lines (VDD, GND) ofdifferent voltages, each supply line being shared between the memorycell and one of the adjacent memory cells, and placed on a common edgebetween the two memory cells.
 4. The memory block of claim 3, whereinthe supply lines (VDD, GND) are of level two, parallel to the bit line(BL0, {overscore (BL0)}), and orthogonal to the word lines (WL00, WL01,WL02, WL03).
 5. The memory block of claim 2, wherein each memory cell,arranged between two other memory cells of the same row, comprises fourN-channel MOS transistors (M1, M2, NI1, NI2) having their sources (SM1,SM2, SNI1, SNI2) and drains (DM1, DM2, DNI1, DNI2) formed in a sameactive area and aligned along a common edge between the memory cell andone of the adjacent memory cells.
 6. The memory block of claim 2,wherein each memory cell, arranged between two other memory cells of thesame row, comprises two P-channel MOS transistors (PI1, PI2) havingtheir sources (SPI1, SPI2) and drains (DPI1, DPI2) aligned along acommon edge between the memory cell and one of the adjacent memorycells.
 7. The memory block of claim 2, wherein the memory cells comprisea conductive strip (30) of level two, perpendicular to the word lines(WL00, WL01, WL02, WL03), connected to one of the word lines (WL00,WL01, WL02, WL03) and to two MOS transistors (M1, M2).
 8. The memoryblock of claim 2, wherein each memory cell comprises a transistor (M1,M2) connected to the bit line (BL0, {overscore (BL0)}), and a metalstrip (31, 32, 46, 47) of level one connecting a transistor (M1, M2) toa bit line (BL0, {overscore (BL0)}) located on an adjacent cell of thesame row.
 9. The memory block of claim 3, wherein each memory cell,arranged between the two other memory cells of the same column,comprises a metal strip (31, 32, 46, 47) of level one, connecting atransistor (M1, M2, PI1, PI2) to a supply line (VDD) or to a bit line(BL0, {overscore (BL0)}), the metal strip being shared between thememory cell and one of the adjacent memory cells, and placed on a commonedge between the two memory cells.
 10. The memory block of claim 6,wherein at least one memory cell comprises a conductive strip of leveltwo (GBL0, {overscore (GBL0)}), parallel to the bit line (BL0,{overscore (BL0)}) and located above the P-channel MOS transistors (PI1,PI2).
 11. A memory formed of a network of rows and columns of memoryblocks defined according to any of claims 1 to 10, wherein the wordlines associated with memory cell rows of memory blocks of a same memoryblock row are common, and wherein the bit lines associated with memorycell columns of memory blocks of a same memory block column areseparate, and comprising, per memory block column, at least oneadditional bit line extending in the column direction and being likelyto be connected to one of the adjacent bit lines.